Intel Lays Out Server Platform Roadmap at IDF
- By Scott Bekker
- September 09, 2004
Intel used its annual developer forum this week to lay out a server platform roadmap that has its Xeon and Itanium server processor lines running on a common platform architecture sometime after 2006.
Carol Barrett, a director of enterprise platform marketing at Intel, said the most important message at the Intel Developer Forum in San Francisco was to communicate Intel's new focus on platform-level planning as a start for how the company looks at silicon-level planning. "It's in response to our customers saying that there's more to the systems that we need to ship than just a microprocessor or a chipset," Barrett said. A recent shift in Intel's organization to bring chipset planning into platform planning reflects the seriousness of the change, she said.
By converging its Itanium processor family and the Xeon processor family on a common future chipset, Intel hopes to leverage the relative economies of scale of the Xeon line to offer the higher performance Itanium at a much more competitive price. The top-of-the-line Itanium 2 is currently listed at $4,227 per processor in 1,000-unit quantities. The top-of-the-line Xeon MP lists for $3,692.
"We expect Itanium, at that point in time, to deliver twice the performance of Xeon at the same platform cost," Barrett said, in a reference to the common platform's debut. Current plans call for Intel to deliver multi-core processors (meaning more than two processor cores on one chip) at the same time as the common chip set.
Shorter term, Intel has several improvements to bake into its product lines from more cache to dual-core capabilities to 90-nm processes on some chips and 65-nm processes on others.
Later this year, Intel plans to deliver another version of its current "Madison" line of Itanium 2 multi-processing chips that ups the cache to 9 MB and a new dual-processing Itanium 2 version code-named "Fanwood."
Intel's 2005 plan calls for the first two Intel Xeon processors MP based on the 90-nm process. They are code-named "Cranford" and "Potomac." Both chips are slated to include Intel Extended Memory 64 Technology and Intel Enhanced SpeedStep Technology. A new chipset, code-named "Twin Castle," will support those chips with PCI Express and DDR2 memory.
That manufacturing miniaturization will clear the way for the first dual-core Xeon MP processor, code-named "Tulsa." Meanwhile, the Itanium processor family is slated to move to dual-core with a version code-named "Montecito." A follow-on Itanium 2 processor code-named "Montvale" will be the first Itanium processor based on 65-nm process technology.
After those processors come out, Intel hopes to move to the common platform architecture with multi-core Xeons and Itaniums. The Xeon is code-named "Whitefield." The Itanium is code-named "Tukwila."
Intel also disclosed "Irwindale," a code-name for a 2005 deliverable in the Intel Xeon DP line. Irwindale will be an incremental step up with a faster clock speed and larger 2-MB cache.
Scott Bekker is editor in chief of Redmond Channel Partner magazine.